Small Signal Analysis Tutorial
Transistor amplifiers amplify an AC input signal that alternates between some maximum positive value and an opposite negative value. To achieve this, a common emitter amplifier circuit configuration needs to be “preset” so that a bipolar junction transistor (BJT) can operate between these two maximum or peak values. This is achieved using a process known as Biasing.
Biasing is very important in amplifier design as it establishes the correct operating conditions of the transistor amplifier ready to receive signals, thereby reducing any distortion to the output signal. Also, the use of a static or DC load line drawn onto the output characteristics curves of an amplifier allows us to see all the possible operating points of the transistor from fully “ON” to fully “OFF”, and to which the quiescent operating point or Q-point of the amplifier can be found.
The aim of any small signal amplifier is to amplify all of the input signal with the minimum amount of distortion possible to the output signal; in other words, the output signal must be an exact reproduction of the input signal but only bigger (amplified). To obtain low distortion when used as an amplifier the operating quiescent point needs to be correctly selected. This is in fact the DC operating point of the amplifier and its position may be established at any point along the load line by a suitable biasing arrangement.
The best possible position for this Q-point is as close to the center position of the load line as reasonably possible, thereby producing a Class A type amplifier operation, i.e. Vce = 1/2Vcc. Consider the Common Emitter Amplifier circuit shown below.
The Common Emitter Amplifier Circuit
The single stage common emitter amplifier circuit shown above uses what is commonly called “Voltage Divider Biasing”. This type of biasing arrangement uses two resistors as a potential divider network across the supply with their center point supplying the required Base bias voltage to the transistor. Voltage divider biasing is commonly used in the design of bipolar transistor amplifier circuits.
This method of biasing the transistor greatly reduces the effects of varying Beta, ( β ) by holding the Base bias at a constant steady voltage level allowing for best stability. The quiescent Base voltage (Vb) is determined by the potential divider network formed by the two resistors, R1, R2 and the power supply voltage Vcc as shown with the current flowing through both resistors.
Then the total resistance RT will be equal to R1 + R2 giving the current as i = Vcc/RT. The voltage level generated at the junction of resistors R1 and R2 holds the Base voltage (Vb) constant at a value below the supply voltage.
The potential divider network used in the common emitter amplifier circuit divides the supply voltage in proportion to the resistance. This bias reference voltage can be easily calculated using the simple voltage divider formula below:
Transistor Bias Voltage
As the same supply voltage, (Vcc) also determines the maximum Collector current, Ic when the transistor is switched fully “ON” (saturation), Vce = 0. The Base current Ib for the transistor is found from the Collector current, Ic and the DC current gain Beta, β of the transistor.
Common Emitter Amplifier Gain (Beta)
A bipolar transistor’s Beta value, sometimes referred to as hFE on manufacturers datasheets, defines the transistor’s forward current gain in its common emitter configuration. The Beta value is an electrical parameter built into the transistor during manufacture. Beta (hFE) has no units as it is a fixed ratio of the two currents, collector current (Ic) and base current (Ib). Thus a small change in the Base current will cause a large change in the Collector current flowing through the transistor.
One final point about Beta. Transistors of the same type and part number will have large variations in their Beta value. For example, the BC107 NPN Bipolar transistor can have a DC current gain Beta value of between 110 and 450 (data sheet value).
That is, one BC107 device may have a Beta value of 110, while another one may have a Beta value of 450, but they are both sold as BC107 npn transistors. The reason for this is that the value of Beta ( β ) is an inherent characteristic of the transistor’s construction and not of its operation.
As the Base/Emitter junction is forward-biased, the Emitter voltage, Ve will be one junction voltage drop different to the Base voltage. If the voltage across the Emitter resistor is known then the Emitter current, Ie can be easily calculated using Ohm’s Law. The Collector current, Ic can be approximated, since it is almost the same value as the Emitter current.
Common Emitter Amplifier Example No1
A common emitter amplifier circuit has a load resistance, RL of 1.2kΩ and a supply voltage of 12v. Calculate the maximum Collector current (Ic) flowing through the load resistor when the transistor is switched fully “ON” (saturation), assume Vce = 0.
Also find the value of the Emitter resistor, RE if it has a voltage drop of 1v across it. Calculate the values of all the other circuit resistors assuming a standard NPN silicon transistor.
This then establishes point “A” on the Collector current vertical axis of the characteristics curves and occurs when Vce = 0. When the transistor is switched fully “OFF”, there is no voltage drop across either resistor RE or RL as no current is flowing through them. Then the voltage drop across the transistor, Vce is equal to the supply voltage, Vcc. This establishes point “B” on the horizontal axis of the characteristics curves.
Generally, the quiescent Q-point of the amplifier is with zero input signal applied to the Base, so the Collector sits about half-way along the load line between zero volts and the supply voltage, (Vcc/2). Therefore, the Collector current at the Q-point of the amplifier will be given as:
This static DC load line produces a straight line equation whose slope is given as: -1/(RL + RE) and that it crosses the vertical Ic axis at a point equal to Vcc/(RL + RE). The actual position of the Q-point on the DC load line is determined by the mean value of Ib.
As the Collector current, Ic of the transistor is also equal to the DC gain of the transistor (Beta), times the Base current (β*Ib), if we assume a Beta (β) value for the transistor of say 100, (one hundred is a reasonable average value for low power signal transistor) the Base current Ib flowing into the transistor will be given as:
Instead of using a separate Base bias supply, it is usual to provide the Base Bias Voltage from the main supply rail (Vcc) through a dropping resistor, R1. Resistors, R1 and R2 can now be chosen to give a suitable quiescent Base current of 45.8μA or 46μA rounded off to the nearest integer.
The current flowing through the potential divider circuit has to be large compared to the actual Base current, Ib, so that the voltage divider network is not loaded by the Base current flow.
A general rule of thumb is a value of at least 10 times Ib flowing through the resistor R2. Transistor Base/Emitter voltage, Vbe is fixed at 0.7V (silicon transistor) then this gives the value of R2 as:
If the current flowing through resistor R2 is 10 times the value of the Base current, then the current flowing through resistor R1 in the divider network must be 11 times the value of the Base current. That is: IR2 + Ib.
Thus the voltage across resistor R1 is equal to Vcc - 1.7v (VRE + 0.7 for silicon transistor) which is equal to 10.3V, therefore R1 can be calculated as:
The value of the Emitter resistor, RE can be easily calculated using Ohm’s Law. The current flowing through RE is a combination of the Base current, Ib and the Collector current Ic and is given as:
Resistor, RE is connected between the transistor’s Emitter terminal and ground, and we said previously that there is a voltage drop of 1 volt across it. Thus the value of the Emitter resistor, RE is calculated as:
So for our simple example above, the preferred values used for the calculated resistors chosen to give a tolerance of 5% (E24) are:
- R1 = 220kΩ
- R2 = 3.9kΩ
- RL = 1.2kΩ
- RE = 22Ω
Then, our original Common Emitter Amplifier circuit above can be rewritten to include the values of the components that we have just calculated above.
Completed Common Emitter Circuit
In Common Emitter Amplifier circuits, capacitors C1 and C2 are used as Coupling Capacitors to separate the AC signals from the DC biasing voltage. This ensures that the bias condition set up for the circuit to operate correctly is not affected by any additional amplifier stages, as the capacitors will only pass AC signals and block any DC component. The output AC signal is then superimposed on the biasing of the following stages. Also a bypass capacitor, CE is included in the Emitter leg circuit.
This capacitor is effectively an open circuit component for DC biasing conditions, which means that the biasing currents and voltages are not affected by the addition of the capacitor maintaining a good Q-point stability.
However, this parallel connected bypass capacitor effectively becomes a short circuit to the Emitter resistor at high frequency signals due to its reactance. Thus only RL plus a very small internal resistance acts as its load increasing voltage gain to its maximum. Generally, the value of the bypass capacitor, CE is chosen to provide a reactance of at most, 1/10th the value of RE at the lowest operating signal frequency.
Output Characteristics Curves
Ok, so far so good. We can now construct a series of curves that show the Collector current, Ic against the Collector/Emitter voltage, Vce with different values of Base current, Ib for our simple common emitter amplifier circuit.
These curves are known as the “Output Characteristic Curves” and are used to show how the transistor will operate over its dynamic range. A static or DC load line is drawn onto the curves for the load resistor RL of 1.2kΩ to show all the transistor’s possible operating points.
When the transistor is switched “OFF”, Vce equals the supply voltage Vcc and this is point “B” on the line. Likewise, when the transistor is fully “ON” and saturated the Collector current is determined by the load resistor, RL and this is point “A” on the line.
We calculated before from the DC gain of the transistor that the Base current required for the mean position of the transistor was 45.8μA and this is marked as point Q on the load line which represents the Quiescent point or Q-point of the amplifier. We could quite easily make life easy for ourselves and round off this value to 50μA exactly, without any effect to the operating point.
Point Q on the load line gives us the Base current Q-point of Ib = 45.8μA or 46μA. We need to find the maximum and minimum peak swings of Base current that will result in a proportional change to the Collector current, Ic without any distortion to the output signal.
As the load line cuts through the different Base current values on the DC characteristics curves we can find the peak swings of Base current that are equally spaced along the load line. These values are marked as points “N” and “M” on the line, giving a minimum and a maximum Base current of 20μA and 80μA respectively.
These points, “N” and “M” can be anywhere along the load line that we choose as long as they are equally spaced from Q. This then gives us a theoretical maximum input signal to the Base terminal of 60μA peak-to-peak, (30μA peak) without producing any distortion to the output signal.
Any input signal giving a Base current greater than this value will drive the transistor to go beyond point “N” and into its “cut-off” region or beyond point “M” and into its Saturation region thereby resulting in distortion to the output signal in the form of “clipping”.
Using points “N” and “M” as an example, the instantaneous values of Collector current and corresponding values of Collector-emitter voltage can be projected from the load line. It can be seen that the Collector-emitter voltage is in anti-phase (-180o) with the collector current.
As the Base current Ib changes in a positive direction from 50μA to 80μA, the Collector-emitter voltage, which is also the output voltage decreases from its steady state value of 5.8 volts to 2.0 volts.
Then a single stage Common Emitter Amplifier is also an “Inverting Amplifier” as an increase in Base voltage causes a decrease in Vout and a decrease in Base voltage produces an increase in Vout. In other words, the output signal is 180o out-of-phase with the input signal.
Common Emitter Voltage Gain
The Voltage Gain of the common emitter amplifier is equal to the ratio of the change in the input voltage to the change in the amplifier’s output voltage. Then ΔVL is Vout and ΔVB is Vin. But voltage gain is also equal to the ratio of the signal resistance in the Collector to the signal resistance in the Emitter and is given as:
We mentioned earlier that as the ac signal frequency increases the bypass capacitor, CE starts to short out the Emitter resistor due to its reactance. Then at high frequencies RE = 0, making the gain infinite.
However, the bipolar transistor has a small internal resistance built into its Emitter region called r’e. The transistor’s semiconductor material offers an internal resistance to the flow of current through it and is generally represented by a small resistor symbol shown inside the main transistor symbol.
Transistor data sheets tell us that for a small signal bipolar transistor this internal resistance is the product of 25mV ÷ Ie (25mV being the internal volt drop across the Emitter junction layer), then for our common Emitter amplifier circuit above this resistance value will be equal to:
This internal Emitter leg resistance will be in series with the external Emitter resistor, RE, then the equation for the transistor’s actual gain will be modified to include this internal resistance so will be:
At low frequency signals the total resistance in the Emitter leg is equal to RE + r’e. At high frequency, the bypass capacitor shorts out the Emitter resistor leaving only the internal resistance r’e in the Emitter leg resulting in a high gain.
Then for our common emitter amplifier circuit above, the gain of the circuit at both low and high signal frequencies is given as:
Amplifier Gain at Low Frequencies
Amplifier Gain at High Frequencies
Thus at very low input signal frequencies, the reactance of the capacitor (XC) is high so the external emitter resistance, RE has an effect on voltage gain lowering it to, in this example, 5.32. However, when the input signal frequency is very high, the reactance of the capacitor shorts out RE (RE = 0) so the amplifier’s voltage gain increases to, in this example, 218.
One final point, the voltage gain is dependent only on the values of the Collector resistor, RL and the Emitter resistance, (RE + r’e) it is not affected by the current gain Beta, β (hFE) of the transistor.
SEPIC Converter Small Signal Analysis
Over the past several decades, the single-ended primary inductance converter (SEPIC) has become a popular topology that finds uses in applications such as distributed power systems and battery chargers. This topology also has an inherent advantage over a boost converter by having a DC blocking capacitor in the power path. This capacitor provides some degree of isolation between the input and output voltages, thereby protecting the system should the converter output be shorted. Since this topology requires two inductors, one may argue that there is no advantage of using a SEPIC over a flyback. The leakage inductance of a flyback transformer, however, will create ringing that needs to be snubbed. This leakage inductance is of little or no consequence in a SEPIC since the switch voltages are clamped by capacitors. Lower switch-node ringing also leads to lower EMI. While the SEPIC has many attractive DC characteristics, its small signal behavior is not well known.
A simplistic view of DC-to-DC converters is that they are a feedback control system comprised of a voltage reference and a feedback loop. In order for this system to be stable and meet transient and steady state requirements, each component in the feedback loop should be analyzed so the proper components may be selected.
The general steps for designing a feedback loop are:
- Analyzing the small signal characteristics of the power stage.
- Compensating the feedback loop based on step 2.
- Simulating the feedback loop using computational software.
- Repeating steps 3 and 4 if necessary.
- Repeating steps 1 through 6 if necessary.
There are many small signal models of the PWM switch, however, the most useful for our purposes is Vorperian’s [1] circuit based model. This model provides physical insight and an intuitive nature to a converters' analysis. This treatment of the small signal characteristics of the SEPIC will be limited to the control-to-output transfer function of a converter operating in continuous conduction mode (CCM), since this is typically of greatest interest.
This expression is unwieldy and is useful only for analysis. By inspection, it is apparent that compensation will be a challenging task. Therefore, in order to simplify the design, it is necessary to either change the circuit or control scheme. Changing the circuit is typically not an option since it adds cost and/or complexity.
From this figure, the systems perspective of current mode control is readily apparent. This is the closed loop current gain multiplied by the output impedance. The closed loop current gain is expressed in terms of an ideal closed loop current gain [The ideal closed loop gain assumes infinite open loop gain. ] multiplied by a discrepancy factor that accounts for non-infinite current loop gain. Expressing the relationship in this form allows one to see the salient features of current mode control. These characteristics include peaking at half the switching frequency for small values of mc and a pole determined by the output capacitor and load.
At this point it would seem reasonable to revise our approach and solve for the current gain Ai including the effect of output capacitor equivalent series resistance (ESR). One will find, however, that the effect of output capacitor ESR on the discrepancy factor is negligible. Another approximation is to simply use the low frequency gain, kd , in place of the entire Ai transfer function or disregard the discrepancy factor entirely. This is adequate for most applications.
As the value of mc increases, the complex pole pair at half the switching frequency split and the response takes on the characteristics of voltage mode control.
For VIN = 3.3V, the power stage control-to-output frequency response has a low frequency gain of 40 dB, real pole and zero at 320 Hz and 16 kHz respectively. Based on this, we may now choose the compensator pole and zero locations to achieve the desired response. For example, if a crossover frequency of 3.5 kHz and a phase margin of 80° are desired, the error amplifier real pole and zero may be placed at 30 Hz and 4 kHz respectively. Using these component values the crossover frequency and phase margin are calculated as 3.4 kHz and 80° respectively. The component selection process may be iterated until the desired crossover frequency and phase margin are reached, however, one should not become concerned with being entirely exact in the calculation of component values.
From this figure it can be seen that the crossover frequency is approximately 3.2 kHz and the phase margin is 80°. As stated, one should not be overly concerned with discrepancies in designing the loop gain because of parasitic elements in the physical system and inaccuracies in measurement. For example, in the Figure above it can be seen that the gain drops dramatically below 1.2 kHz. This drop in gain is due to the frequency response of the transformer used for voltage injection.
It has been shown that the SEPIC used in voltage mode control has an unruly response that may be alleviated by use of current mode control.
Additional Notes on Small-Signal Analysis
- Find the quiescent point (DC operating point) of the circuit.
- Linearize the non-linear circuit components at the DC operating point. The most basic example of this is a diode, whose current is approximately proportional to the square of the voltage across it. But as long as the signal is small (hence the name, small-signal analysis!) compared to the DC operating point of the diode, you can approximate this to a linear relationship, i.e. ΔV=ΔIR \Delta V = \Delta I R.
- Find the small-signal solution: Now the DC sources are removed. Voltage sources are replaced with 0Ω0\Omega resistors (short circuit), current sources are replaced with ∞Ω\infty \Omega resistors (open circuit).